1 commercial and industrial temperature ranges idt23s05 3.3v zero delay clock buffer, spread spectrum august 2010 2010 integrated device technology, inc. dsc 6381/7 c commercial and industrial temperature ranges the idt logo is a registered trademark of integrated device technology, inc. fea tures: ? phase-lock loop clock distribution ? 10mhz to 133mhz operating frequency ? distributes one clock input to one bank of five outputs ? zero input-output delay ? output skew < 250ps ? low jitter <200 ps cycle-to-cycle ? idt23s05-1 for standard drive ? idt23s05-1h for high drive ? no external rc network required ? operates at 3.3v v dd ? power down mode ? spread spectrum compatible ? available in soic package functional block diagram idt23s05 3.3v zero dela y clock buffer, spread spectrum comp a tible pll 8 clk1 clk2 clk3 clk4 control logic ref clkout 1 32 57 description: the idt23s05 is a high-speed phase-lock loop (pll) clock buffer, designed to address high-speed clock distribution applications. the zerodelay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133mhz. the idt23s05 is an 8-pin version of the idt23s09. idt23s05 accepts one reference input, and drives out five low skew clocks. the -1h versionof this device operates up to 133mhz frequency and has a higher drive than the -1 device. all parts have on-chip plls which lock to an input clock on the ref pin. the pll feedback is on-chip and is obtained from the clkout pad. in the absence of an input clock, the idt23s05 enters power down. in this mode, the device will draw less than 12 a for commercial tempera- ture range and less than 25 a for industrial temperature range , the outputs are tri-stated, and the pll is not running, resulting in a significant reductionof power. the idt23s05 is characterized for both industrial and commercial operation.
2 commercial and industrial temperature ranges idt23s05 3.3v zero delay clock buffer, spread spectrum ref clk1 2 34 8 76 5 1 clk2 gnd clkout clk4 v dd clk3 pin configura tion soic top view symbol rating max. unit v dd supply voltage range ?0.5 to +4.6 v v i (2) input voltage range (ref) ?0.5 to +5.5 v v i input voltage range ?0.5 to v (except ref) v dd +0.5 i ik (v i < 0) input clamp current ?50 ma i o (v o = 0 to v dd ) continuous output current 50 ma v dd or gnd continuous current 100 ma t a = 55c maximum power dissipation 0.7 w (in still air) (3) t stg storage temperature range ?65 to +150 c operating commercial temperature 0 to +70 c temperature range operating industrial temperature -40 to +85 c temperature range notes:1. stresses greater than those listed under absolute maximum ratings may causepermanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. the input and output negative-voltage ratings may be exceeded if the input and outputclamp-current ratings are observed. 3. the maximum package power dissipation is calculated using a junction temperatureof 150c and a board trace length of 750 mils. notes:1. weak pull down. 2. weak pull down on all outputs. pin description absol ute maximum ra tings (1) applica tions: ? sdram ? t elecom ? datacom ? pc motherboards/workstations ? critical path delay designs pin name pin number type functional description ref (1) 1 in input reference clock, 5 volt tolerant input clk2 (2) 2 out output clock clk1 (2) 3 out output clock gnd 4 ground ground clk3 (2) 5 out output clock v dd 6 pwr 3.3v supply clk4 (2) 7 out output clock clkout (2) 8 out output clock, internal feedback on this pin
3 commercial and industrial temperature ranges idt23s05 3.3v zero delay clock buffer, spread spectrum symbol parameter min. max. unit v dd supply voltage 3 3.6 v t a operating temperature (ambient temperature) 0 70 c c l load capacitance < 100mhz ? 30 pf load capacitance 100mhz - 133mhz ? 10 c in input capacitance ? 7 pf opera ting conditions - commer cial dc electrical characteristics - commercial symbol parameter conditions min. max. unit v il input low voltage level ? 0.8 v v ih input high voltage level 2 ? v i il input low current v in = 0v ? 50 a i ih input high current v in = v dd ? 100 a v ol output low voltage standard drive i ol = 8ma ? 0.4 v high drive i ol = 12ma (-1h) v oh output high voltage standard drive i oh = -8ma 2.4 ? v high drive i oh = -12ma (-1h) i dd_pd power down current ref = 0mhz ? 12 a i dd supply current unloaded outputs at 66.66mhz ? 32 ma swit ching chara cteristics (23s05-1) - commer cial (1,2) symbol parameter conditions min. typ. max. unit t 1 output frequency 10pf load 10 ? 133 mhz 30pf load 10 ? 100 duty cycle = t 2 t 1 measured at 1.4v, f out = 66.66mhz 40 50 60 % t 3 rise time measured between 0.8v and 2v ? ? 2.5 ns t 4 fall time measured between 0.8v and 2v ? ? 2.5 ns t 5 output to output skew all outputs equally loaded ? ? 250 ps t 6 delay, ref rising edge to clkout rising edge measured at v dd /2 ? 0 350 ps t 7 device-to-device skew measured at v dd /2 on the clkout pins of devices ? 0 700 ps t j cycle-to-cycle jitter, pk - pk measured at 66.66mhz, loaded outputs ? ? 200 ps t lock pll lock time stable power supply, valid clock presented on ref pin ? ? 1 ms notes:1. ref input has a threshold voltage of v dd /2. 2. all parameters specified with loaded outputs.
4 commercial and industrial temperature ranges idt23s05 3.3v zero delay clock buffer, spread spectrum symbol parameter min. max. unit v dd supply voltage 3 3.6 v t a operating temperature (ambient temperature) -40 +85 c c l load capacitance < 100mhz ? 30 pf load capacitance 100mhz - 133mhz ? 10 c in input capacitance ? 7 pf opera ting conditions - industrial swit ching chara cteristics (23s05-1h) - commer cial (1,2) symbol parameter conditions min. typ. max. unit t 1 output frequency 10pf load 10 ? 133 mhz 30pf load 10 ? 100 duty cycle = t 2 t 1 measured at 1.4v, f out = 66.66mhz 40 50 60 % duty cycle = t 2 t 1 measured at 1.4v, f out <50mhz 45 50 55 % t 3 rise time measured between 0.8v and 2v ? ? 1.5 ns t 4 fall time measured between 0.8v and 2v ? ? 1.5 ns t 5 output to output skew all outputs equally loaded ? ? 250 ps t 6 delay, ref rising edge to clkout rising edge measured at v dd /2 ? 0 350 ps t 7 device-to-device skew measured at v dd /2 on the clkout pins of devices ? 0 700 ps t 8 output slew rate measured between 0.8v and 2v using test circuit #2 1 ? ? v/ns t j cycle-to-cycle jitter, pk - pk measured at 66.66mhz, loaded outputs ? ? 200 ps t lock pll lock time stable power supply, valid clock presented on ref pin ? ? 1 ms notes:1. ref input has a threshold voltage of v dd /2. 2. all parameters specified with loaded outputs. dc electrical characteristics - industrial symbol parameter conditions min. max. unit v il input low voltage level ? 0.8 v v ih input high voltage level 2 ? v i il input low current v in = 0v ? 50 a i ih input high current v in = v dd ? 100 a v ol output low voltage standard drive i ol = 8ma ? 0.4 v high drive i ol = 12ma (-1h) v oh output high voltage standard drive i oh = -8ma 2.4 ? v high drive i oh = -12ma (-1h) i dd_pd power down current ref = 0mhz ? 25 a i dd supply current unloaded outputs at 66.66mhz ? 35 ma
5 commercial and industrial temperature ranges idt23s05 3.3v zero delay clock buffer, spread spectrum swit ching chara cteristics (23s05-1h) - industrial (1,2) symbol parameter conditions min. typ. max. unit t 1 output frequency 10pf load 10 ? 133 mhz 30pf load 10 ? 100 duty cycle = t 2 t 1 measured at 1.4v, f out = 66.66mhz 40 50 60 % duty cycle = t 2 t 1 measured at 1.4v, f out <50mhz 45 50 55 % t 3 rise time measured between 0.8v and 2v ? ? 1.5 ns t 4 fall time measured between 0.8v and 2v ? ? 1.5 ns t 5 output to output skew all outputs equally loaded ? ? 250 ps t 6 delay, ref rising edge to clkout rising edge measured at v dd /2 ? 0 350 ps t 7 device-to-device skew measured at v dd /2 on the clkout pins of devices ? 0 700 ps t 8 output slew rate measured between 0.8v and 2v using test circuit #2 1 ? ? v/ns t j cycle-to-cycle jitter, pk - pk measured at 66.66mhz, loaded outputs ? ? 200 ps t lock pll lock time stable power supply, valid clock presented on ref pin ? ? 1 ms notes:1. ref input has a threshold voltage of v dd /2. 2. all parameters specified with loaded outputs. swit ching chara cteristics (23s05-1) - industrial (1,2) symbol parameter conditions min. typ. max. unit t 1 output frequency 10pf load 10 ? 133 mhz 30pf load 10 ? 100 duty cycle = t 2 t 1 measured at 1.4v, f out = 66.66mhz 40 50 60 % t 3 rise time measured between 0.8v and 2v ? ? 2.5 ns t 4 fall time measured between 0.8v and 2v ? ? 2.5 ns t 5 output to output skew all outputs equally loaded ? ? 250 ps t 6 delay, ref rising edge to clkout rising edge measured at v dd /2 ? 0 350 ps t 7 device-to-device skew measured at v dd /2 on the clkout pins of devices ? 0 700 ps t j cycle-to-cycle jitter, pk - pk measured at 66.66mhz, loaded outputs ? ? 200 ps t lock pll lock time stable power supply, valid clock presented on ref pin ? ? 1 ms notes:1. ref input has a threshold voltage of v dd /2. 2. all parameters specified with loaded outputs.
6 commercial and industrial temperature ranges idt23s05 3.3v zero delay clock buffer, spread spectrum zer o dela y and skew contr ol all outputs should be uniformly loaded in order to achieve zero i/o delay. since the clkout pin is the internal feedback for the pll, its relative loading can affect and adjust the input/output delay. for designs utilizing zero i/o delay, all outputs including clkout must be equally loaded. even if the output is not used, it must have a capacitive load equal to that on the other outputs in order to obtain true zero i/o delay. if i/o delay adjustments are needed, use the output load difference diagramto calculate loading differences between the clkout pin and other outputs. for zero output-to-output skew, all outputs must be loaded equally. spread spectr um comp a tible many systems being designed now use a technology called spread spectrum frequency timing generation. this product is designed not to filter off the spread spectrum feature of the reference input, assuming it exists. when a zero delay buffer is not designed to pass the spread spectrum featurethrough, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.
7 commercial and industrial temperature ranges idt23s05 3.3v zero delay clock buffer, spread spectrum v dd outputs v dd gnd gnd 0.1 f 0.1 f v dd outputs 10pf v dd gnd gnd 0.1 f 0.1 f 1k 1k c load clk out clk out output 1.4v 1.4v t5 output ref v dd/ 2 t6 output clk out device 1 t7 clk out device 2 v dd/ 2 v dd /2 v dd /2 1.4v 1.4v t2 t1 1.4v 2v 0.8v t3 t4 0.8v 3.3v 0v 2v output all outputs rise/fall time input to output propagation delay device to device skew output to output skew duty cycle timing swit ching wa veforms test circuit 1 (all parameters except t8) test circuit 2 (t8, output slew rate on -1h devices) test circuits
8 commercial and industrial temperature ranges idt23s05 3.3v zero delay clock buffer, spread spectrum min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.33 0.51 .013 .020 c 0.19 0.25 .0075 .0098 d e 3.80 4.00 .1497 .1574 e h 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 n a 0 8 0 8 variations min max min max 8 4.80 5.00 .1890 .1968 1.27 basic 0.050 basic common dimensions in millimeters in inches common dimensions reference doc.: jedec publication 95, ms-012 150 mil (n arrow body) soic n see variations see variations d mm. d (inch) symbol see variations see variations
9 commercial and industrial temperature ranges idt23s05 3.3v zero delay clock buffer, spread spectrum ordering informa tion idt xxxxx xx x package process device type 23s05-1 23s05-1h zero delay clock buffer with high drive, spread spectrum compatible dc dcg small outline soic - green blank i commercial (0 o c to +70 o c) industrial (-40 o c to +85 o c) corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 clockhelp@idt.com san jose, ca 95138 fax: 408-284-2775www.idt.com part / order number shipping packaging package temperature 23s05-1dcg tubes 8-pin soic 0 to +70 c 23s05-1dcg8 tape and reel 8-pin soic 0 to +70 c 23s05-1dcgi tubes 8-pin soic -40 to +85c 23s05-1dcgi8 tape and reel 8-pin soic -40 to +85c 23s05-1hdcg tubes 8-pin soic 0 to +70 c 23s05-1hdcg8 tape and reel 8-pin soic 0 to +70 c 23S05-1HDCGI tubes 8-pin soic -40 to +85c 23S05-1HDCGI8 tape and reel 8-pin soic -40 to +85c
|
